clock line meaning in English

时钟线

The data and clock lines are both open collector
数据和时钟线都是集电极开路的。
The host has ultimate control over the bus and may inhibit communication at any time by pulling the clock line low
主机对总线有最高的控制权，在任何时候通过将时钟线拉低就可以禁止通信。
The clock line must be continuously high for at least 50 microseconds before the device can begin to transmit its data
如果不是，主机禁止通信，设备必须缓冲任何要发送的数据，直到主机释放时钟。
When the keyboard or mouse wants to send information , it first checks the clock line to make sure it ' s at a high logic level
当键盘或者鼠标想发送数据时，它首先必须检查时钟线，确认它处于高电平。
The host changes the data line only when the clock line is low , and data is read by the device when clock is high
只有当时钟线为低的时候，主机才可以改变数据线（也就是将数据写入到数据线）。数据将在时钟为高电平的时候被设备读取。